Over on the [Behind The Code with Gerry] YouTube channel our hacker [Gerry] reveals us emulate a 74LS48 BCD-to-7-segment decoder/driver utilizing an Altera CPLD Logic Chip From 1998.
That is very a lot a das blinkenlights sort of venture. The objective is to get a 7-segment show to depend from 0 to 9, and that’s it. [Gerry] has a 74LS193 Up/Down Binary Counter, a 74LS42 BCD to Decimal Decoder, and a few 74LS00 NAND gates, however he “doesn’t have” an 74LS48 to drive the 7-segment show so he emulates one with an outdated Altera CPLD mannequin EPM7064SLC44 which dates again to the late nineties. A CPLD is a Complicated Programmable Logic Gadget which is a sort of precursor to FPGA expertise.
This enjoyable video runs for almost one hour and there are all kinds of twists and turns. The clock is made out of a 555 timer. The Altera USB Blaster is used to program the CPLD through JTAG. However earlier than he can try this he has to re-enable JTAG on his CPLD as a result of JTAG LOCKOUT has been used on his secondhand chip. JTAG LOCKOUT is one thing you are able to do so to use the assorted JTAG pins for different functions in your design, at the price of now not being about to entry through JTAG! Fortuitously [Gerry] has the proper gear to do a full reset of his chip and thus reinstate JTAG help.
Simply as he’s almost completed his venture he manages to brief out and destroy his CPLD by dropping a wire into the wall energy socket! Discuss unfortunate! He has to return to the drafting board with an identical mannequin. And ultimately he realizes he used the the 7447 (widespread anode) however truly wanted the 7448 (widespread cathode), so he has to repair that up too. All in all it’s enjoyable to see what was state-of-the-art again in 1998. When you’re excited by such belongings you may wish to learn Not Prepared For FPGAs? Attempt A CPLD.
